The subject application is related to subject matter disclosed in Japanese Patent Application No. 2000-89561 filed on Mar. 28, 2000 in Japan to which the subject application claims priority under Paris Convention and which is incorporated herein by reference.
1. Field of The Invention
The present invention relates generally to a synchronous type semiconductor memory device which operates in a burst mode in synchronism with a clock signal. More specifically, the invention relates to a synchronous type semiconductor memory device wherein a data reading operation corresponding to read latency is accelerated.
2. Related Background Art
As the working speed of CPUs for use in computers is accelerated every year, rapidly operatable SRAMs are often being used as cache memories required to follow the operation of rapid CPUs. In such cases, SRAMs used as cache memories are often synchronous SRAMs which operate in synchronism with external clocks.
In order to allow a more rapid operation than the operation in a usual random access, the following two architectures are sometimes adopted.
First, there is a burst sequence for sequentially automatically generating addresses of a predetermine bit number on the basis of a predetermined sequence in synchronism with clocks in the subsequent operation cycle in accordance with an initial address inputted from the outside. In this burst operation, it is not required to incorporate addresses from the outside every operation cycle, and a rapid operation is realized by assigning the burst address to the fastest system in a memory cell selecting path.
Secondary, there is a read latency which is the setting how many cycles after a cycle in which an address is inputted from the outside, data should be outputted. By increasing the number of cycles, i.e., a read latency, in a predetermined period of time until the initial data are outputted after an address is inputted from the outside, it is possible to increase the operating frequency.
FIG. 1 is a block diagram showing the construction of a conventional synchronous SRAM.
The conventional synchronous SRAM comprises: nxc3x97m memory cells C11, . . . , Cnm provided in the form of a matrix; a row decoder RD for outputting a row selecting signal for selecting one of the memory cells in each row; word lines WL1, . . . , WLn, connected to the memory cells in each row and the row decoder RD, for transmitting the row selecting signal; a column decoder CD for decoding an input address to a column selecting signal for selecting one of the memory cells in each column, to output the column selecting signal; a burst counter BC for sequentially automatically generating an address of a predetermined bit number in synchronism with a clock on the basis of a predetermined sequence in the subsequent operation cycle in accordance with the inputted initial address, to output the generated address to the column decoder; a column register CRG for outputting the column selecting signal, which is inputted from the column decoder CD, at a predetermined timing; column selecting signal lines YS1, . . . , YSm, connected to the column register CRG, for transmitting the column selecting signal; bit line pairs BL1, BL1B, . . . , BLm, BLMB, which are connected to the memory cells in each column and which comprise bit lines and inversion-side bit lines for transmitting a data signal when data are inputted to and outputted from the memory cells; bit line peripheral circuits CA1, . . . , CAm which are connected to the respective bit line pairs and the respective column selecting signal lines and to which the column selecting signal is inputted, the data signal transmitted by the bit line pairs being inputted to and outputted from the bit line bit line peripheral circuits CA1, . . . , CAm; a data bus pair comprising a data bus DL and inversion-side data bus DLB which are connected to the respective bit line pairs via the respective bit line peripheral circuits; a reading circuit RC for reading data out of the respective memory cells via the bit line pairs, the bit line peripheral circuits and data bus pair, to amplify and output the read data; a data output register RGOUT for outputting data, which are amplified by the reading circuit RC, to an input/output port I/O at a predetermined timing; a data input register RGIN for outputting data, which are inputted from the input/output port I/O, at a predetermined timing; and a writing circuit WC for amplifying and outputting data, which are inputted from the data input register RGIN, to write the data in each of the memory cells via the data bus pair, bit line peripheral circuits and bit line pairs.
As an example of the construction of each of the memory cells C11, . . . , Cnm, the construction of the first-row, first-column memory cell C11 will be described. The memory cell C11 comprises: first and second inverters INV11a and INV11b which are connected to each other as a cycle; a first transfer switch TS11 comprising an N-channel MOS transistor which is provided between the first-column bit line BL1 and the input node of the first inverter Inv11a, and the gate of which is connected to the first-row word line WL1; and a first inversion-side transfer switch TS11B comprising an N-channel MOS transistor which is provided between the first-column inversion-side bit line BL1B and the input node of the second inverter INV11b, and the gate of which is connected to the first-row word line WL1. The first and second inverters INV11a and INV11b constitute a flip-flop. Each of the other memory cells has the same construction.
Each of the bit line peripheral circuits CA1, . . . , CAm comprises: a column switch for connecting and disconnecting between the respective bit lines and inversion-side bit lines, and the data bus DL and inversion-side data bus DLB; a pre-charging circuit for pre-charging the respective bit lines and inversion-side bit lines; and an equalizing circuit for equalizing the respective bit lines and inversion-side bit lines. The column selecting signal is inputted to the column switch, so that the connection and disconnection between the respective bit lines and inversion-side bit lines, and the data bus DL and inversion-side data bus DLB is controlled.
FIG. 2 is a timing chart showing the waveforms of principal signals in the conventional synchronous SRAM shown in FIG. 1. The signal waveforms shown in FIG. 2 include the waveforms of a clock signal CLK, an address signal Add, a row selecting signal for the first-row word line WL1, a potential of each of the bit lines BL and inversion-side bit lines BLB, column selecting signals for the column selecting signal lines YS1, YS2, YS3 and YS4, and a data signal DATA in the input/output port I/O.
Referring to FIG. 2, a data reading operation in the conventional synchronous SRAM will be described below.
When an address signal Add is inputted in synchronism with the leading edge of a clock signal CLK at a start time t0 in the initial cycle T1 during a reading operation in a memory cell, decode signals are generated by the row decoder RD and column decoder CD as a row selecting signal and a column selecting signal, respectively.
Assuming herein that a word line selected by the row selecting signal is the first-row word line WL1, the transfer switches of the memory cells C11, C12, . . . , C1m connected to the first-row word line WL1 are turned on by the row selecting signal transmitted by the first-row word line WL1. Then, a current flows into the low potential side of the flip-flops constituting the selected memory cells via the transfer switches. As a result, the potential of one of the bit line pairs BL and BLB, which have been pre-charged at a high potential and equalized, is lowered to cause a potential difference between the pair of bit lines BL and BLB. At this time, the reading circuit RC holds a preparatory state in which data read in the preceding reading operation are canceled.
In the second cycle T2, the column selecting signal generated by the column decoder CD in the first cycle T1 is outputted to the selected column selecting signal line via the column register CRG. Assuming that the selected column selecting signal line is the first column selecting line YS1, the column selecting signal is inputted to the column switch of the first-column bit line peripheral circuit CA1 via the first column selecting signal line YS1, so that the column switch of the first-column bit line peripheral circuit CA1 is turned on. Substantially simultaneously therewith, a minute potential difference caused between the pair of bit lines BL1 and BL1B is propagated to the data bus pair DL and DLB to activate the reading circuit RC to amplify the minute potential difference.
In the third cycle T3, the data DATA amplified by the reading circuit RC are outputted to the input/output port I/O via the data output register RGOUT.
Furthermore, the example of the reading operation shown in FIG. 2 is a reading operation in the case of a read latency of 4.
An operation based on a burst sequence will be described below.
When the initial address is inputted to the column decoder CD, an address of a predetermined bit number is inputted to the burst counter in accordance therewith, so that an address of a predetermined bit number is sequentially automatically generated in synchronism with the clock signal CLK in the subsequent operation cycle. In the example of the reading operation shown in FIG. 2, after the second cycle T2, a column selecting signals is selected in accordance with the initial address on the basis of a predetermined burst sequence. Then, the column selecting signal is outputted via the column register CRG as a column address based on a predetermined burst sequence in or after the next operation cycle, so that the reading operation continues to be carried out in accordance with the column address.
In the above described circuit operation, in order to accelerate the reading operation in the case of the read latency of 4, the following device is added.
After the initial address is incorporated to select the word line, a potential difference between the pair of bit lines is generated, and the potential difference increases with the elapse of time. The reading circuit RC is designed to amplify the potential difference between the pair of bit lines. As the potential difference increases, the operation margin of the reading circuit RC is improved. Since the potential difference xcex94V1 between the pair of bit lines at the initial burst address after selecting the word line is minimum, the operation margin of the reading circuit RC is minimum.
Therefore, two cycles are applied to a reading operation in a memory cell corresponding to the first burst address at which the operation margin is minimum, and one cycle is applied to a reading operation in a memory cell corresponding to the subsequent burst address. The number of cycles based on the operation specification of the read latency, i.e., the number of cycles until data corresponding to the initial address are outputted after the initial address is incorporated, is spent on the data reading cycle corresponding to the initial burst address at which the operation margin is minimum, so that the acceleration of the reading operation is realized.
However, since a special sequence is adopted for only the reading operation corresponding to the initial address without reading all of output data are in the same operation sequence, the number of elements, which must be taken into consideration in the operation analysis, increases to complicate the analysis, so that there is a problem in that the system circuit and the setting of the internal timing are complicated.
In the above described reading operation, during the operation based on the burst sequence, the word line continues to be selected until the burst sequence of predetermined bits is completed. Since current continues to flow through the memory cells while the word line is selected, there is also a problem in that current consumption increases.
It is therefore an object of the present invention to realize the simplification of a system circuit and the facilitation of an operation analysis according thereto, by using the same sequence as a reading operation in each of operation cycles based on a burst sequence corresponding to a read latency.
It is another object of the present invention to provide a synchronous memory capable of corresponding to a plurality of read latencies and rapidly operating in a burst mode.
It is a further object of the present invention to reduce the current consumption of memory cells during a reading operation based on a burst sequence.
According to the present invention, there is provided with a semiconductor memory device comprising:
a plurality of memory cell sub-array groups, each of which comprises a memory cell sub-array including a plurality of memory cells which are arranged at cross portions of a plurality of bit line pairs and a plurality of local word lines, a local row decoder for transmitting a row selecting signal for selecting each row of said memory cell sub-array, and a bit line peripheral circuit group including a plurality of bit line peripheral circuits which are connected to said bit line pairs of said memory cell sub-array, respectively, and to and from which said data signal transmitted by said bit line pairs are inputted and outputted;
a global row decoder for decoding an inputted address to a row selecting signal for selecting the memory cells in each row of each of the memory cell sub-arrays, to output said row selecting signal to each of said local row decoders via a global word line;
a column decoder for decoding said input address to a column selecting signal for selecting the memory cells in each column of each of said memory cell sub-arrays, to output said column selecting signal to each of said bit line peripheral circuits via a plurality of column selecting signal lines;
a block decoder for decoding said inputted address to a first block selecting signal, which is the base of a signal for selecting each of said memory cell sub-arrays, to output said first block selecting signal;
a burst counter for sequentially automatically generating an address of a predetermined bit number in synchronism with a clock on the basis of a predetermined sequence in the subsequent operation cycle in accordance with the inputted initial address, to output the generated address to said block decoder;
a plurality of block decoder selection-time adjusting circuits for sequentially outputting said first block selecting signal, which is inputted from said block decoder, as a second block selecting signal at a timing corresponding to a read latency and for outputting said first block selecting signal as a third block selecting signal which is a signal having a length corresponding to said read latency and which is inputted to each of said local row decoders to controls the transmission of said row selecting signal based on each of said local row decoders;
a plurality of block switches, each of which is connected to said bit line peripheral circuits of a corresponding one of said bit line peripheral circuit groups via a local data line pair and which controls the propriety of the input/output of data via said local data line pair in response to the input of said second block selecting signal;
a data bus pair which is connected to each of said bit line pairs via a corresponding one of said block switches; and
a reading circuit for reading data out of each of said memory cells via said bit line pairs, bit line peripheral circuits, local data line pairs, block switches and data bus pair, to amplify and output the read data.
In summary, according to a semiconductor memory device of the present invention, the reading operation in each of operation cycles based on a burst sequence corresponding to a read latency is the same sequence, so that it is possible to realize the simplification of a system circuit and the facilitation of an operation analysis according thereto. It is also possible to provide a synchronous memory capable of corresponding to a plurality of read latencies and rapidly operating in a burst mode. Moreover, it is possible to reduce the current consumption of memory cells during a reading operation based on a burst sequence.